Document ID: 10481
Contents
Introduction
Prerequisites
Requirements
Components Used
Conventions
PA-A1 Architecture
PA-A1 Error Counters
PA-A1 Performance Issues on the Cisco 7200 Series
Memory Fallbacks and the PA-A1
Known Issues
RxFREEZE Errors
False Throttles With Token Ring PA
Related Information
Introduction
Cisco offers three ATM port adapters for 7x00 series routers. The PA-A1 port adapter is designed for use as an ATM LAN adapter. The PA-A1 is also known as ATM Lite. To determine whether you have a PA-A1, issue the show diag command:
PA Bay 1 Information: ATM LITE PA, 1 ports, PA-A1-OC3MM EEPROM format version 1 HW rev 1.01, Board revision A0 Serial number: 10744404 Part number: 73-1843-03
This document reviews the architecture of the PA-A1 and provides troubleshooting steps for architecture-related issues on the PA-A1. In addition, this document explains the meaning of the input error counters displayed in show interface atm output.
Prerequisites
Requirements
There are no specific requirements for this document.
Components Used
The information in this document is based on the Cisco PA-A1 ATM port adapter.
The information in this document was created from the devices in a specific lab environment. All of the devices used in this document started with a cleared (default) configuration. If your network is live, make sure that you understand the potential impact of any command.
Conventions
For more information on document conventions, refer to the Cisco Technical Tips Conventions.
PA-A1 Architecture
The PA-A1 uses a TI1570 segmentation and reassembly (SAR) chip. Output from the show interface atm command displays the name of the SAR:
router# show interface atm3/0
ATM3/0 is up, line protocol is up
Hardware is TI1570 ATM
MTU 1500 bytes, sub MTU 1500, BW 20000 Kbit, DLY 80 usec, rely 255/255,
load 105/255
Encapsulation ATM, loopback not set, keepalive not supported
Encapsulation(s): AAL5, PVC mode
2048 maximum active VCs, 1024 VCS per VP, 8 current VCCs
VC idle disconnect time: 300 seconds
Signalling vc = 90, vpi = 0, vci = 5
UNI Version = 3.1, Link Side = user
Last input 00:00:00, output 00:00:00, output hang never
Last clearing of "show interface" counters 00:08:41
Queueing strategy: fifo
Output queue 0/2048, 0 drops; input queue 0/2048, 0 drops
5 minute input rate 8234000 bits/sec, 1891 packets/sec
5 minute output rate 8271000 bits/sec, 1758 packets/sec
949143 packets input, 507193928 bytes, 0 no buffer
Received 0 broadcasts, 0 runts, 0 giants, 0 throttles
541 input errors, 0 CRC, 0 frame, 52 overrun, 0 ignored, 544 abort
879593 packets output, 528929340 bytes, 0 underruns
0 output errors, 0 collisions, 0 interface resets
0 output buffer failures, 0 output buffers swapped out
This diagram illustrates the path that bits take when the PA-A1 receives them on the physical wire. There are various locations inside the system where either a cell or a reassembled packet can be stored.
Consider this process:
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When a cell arrives at the ATM interface, the TI1500 framer chip stores the cell in its first-in-first-out (FIFO) memory. This memory is three cells deep, and each receive (Rx) cell FIFO is 48 bytes for storing the payload of a single cell.
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The cell then moves to the FIFO memory of the TI1570 SAR, which is eight cells deep.
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Finally, the cell moves across the Peripheral Component Interconnect (PCI) bus and into the receive buffers in packet memory on the Versatile Interface Processor (VIP) of a Cisco 7500 router or on the Network Processing Engine (NPE)/Network Services Engine (NSE) of a Cisco 7200 router. Once the cells are in host memory, the PA-A1 driver reassembles and processes them.
The important point about this architecture is that the PA-A1 itself provides shallow FIFO memory that holds only a few cells. The PA-A1 relies on the host memory to reassemble the received packets. Thus, the PA-A1 increases the amount of PCI bus activity, since all received cells must be copied into host memory. Passing cells rather than reassembled frames across the PCI bus is called cell-mode processing.
PA-A1 Error Counters
The PA-A1’s cell-processing architecture is similar to hardware version 1.0 of the PA-A3. In some cases, it may lead to input errors, as displayed in the output of the show interface command. This list defines the meaning of each input error counter:
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ignored—Counts the number of times that the SAR’s receive buffers were full.
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overrun—Counts the number of times that the framer’s receive cell FIFO was full and a newly arrived cell was dropped. Overruns are usually a symptom that other resources—such as the SAR’s FIFO and the PCI bus—are full or busy. In other words, a full receive cell FIFO on the SAR can lead to a full FIFO on the framer.
The overrun counter does not include the number of dropped cells or packets. Rather, it counts the number of times that the PA-A1 driver detected a receive cell FIFO overrun condition.
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abort—Counts the number of times that a cell was dropped due to a receive cell FIFO overrun. More specifically, aborts are packet drops caused by cell throttling, at the microcode level, to alleviate framing overruns. Thus, aborts stem from overruns, and you might see both counters increment on the ATM interface. Aborts point to congestion on the PCI bus.
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CRC—Counts the number of times that the reassembled packet failed the ATM adaptation layer 5 (AAL5) trailer’s cyclic redundancy check-32 (CRC-32). CRC-32 errors typically occur when one or more cells of a packet have been lost due to one of these reasons:
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Cells were lost during transmission in the ATM cloud. In this case, only the CRC counter increments.
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Cells were dropped by the PA-A1 when it experienced a receive cell FIFO overrun. In this case, both the CRC counter and the abort counter increment.
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If your PA-A1 is reporting input errors, try these steps to resolve the problem:
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Try replacing the PA-A1 with a hardware revision 2 PA-A3.
The onboard memory of the PA-A3 allows it to better handle bursts of traffic.
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Characterize the traffic patterns.
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Is the PA-A1 receiving very “bursty” traffic close to wire-rate speeds within a very small timeframe?
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Is the interface receiving a lot of broadcasts?
Issue the show atm vc [vcd] command to see the number of broadcasts received.
router# show atm vc 38 ATM3/0.38: VCD: 38, VPI: 1, VCI: 38, etype:0x0, AAL5 - LLC/SNAP, Flags:0x40C30 PeakRate: 0, Average Rate: 0, Burst Cells: 0, VCmode: 0x0 OAM DISABLED, InARP frequency: 15 minute(s) InPkts: 102544, OutPkts: 5814653, InBytes: 8784421, OutBytes: 2464465236 InPRoc: 20483, OutPRoc: 118, Broadcasts: 5715541 !--- Many Broadcasts. InFast: 82061, OutFast: 98583, InAS: 0, OutAS:0 !--- Few OutFast packets. OAM F5 cells sent: 0, OAM cells received: 0 Status: ACTIVE
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How many packets used the “Processor” switching path—and were process-switched—and how many packets used the “Route cache” switching path—and were switched using some faster method, like fast switching or Cisco Express Forwarding (CEF)?
Issue these commands to characterize the Cisco IOS® Software switching method most frequently used on the ATM interface:
router# show interface atm3/0 accounting ATM3/0 Protocol Pkts In Chars In Pkts Out Chars Out IP 11668823 367032142 19641534 3385588141 ARP 0 0 78 2496 router# show interface atm2/0/0 statistics ATM2/0/0 Switching path Pkts In Chars In Pkts Out Chars Out Processor 669801 181603242 550484 40233668 Route cache 259706 161595970 293539623 3173437503 Distrib cache 368473916 4288673940 46134582 3901241354 Total 369403423 336905856 340224693 2819945925
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In a VIP, use the PA-A1 alone and leave the other port adapter slot empty.
Doing this means that the PA-A1 does not need to compete with a second port adapter for VIP host memory resources or for access to the PCI bus that crosses the length of the VIP. Aborts and overruns can occur when the PCI bus is congested and received cells cannot be moved from the PA-A1’s FIFO memory to the VIP memory quickly enough (compared with the incoming cell rate). PCI bus congestion can also occur when the PA-A1 must process a burst of transmit activity simultaneously, because the receive and transmit activities share the PCI bus.
PA-A1 Performance Issues on the Cisco 7200 Series
Cisco 7200 series routers use two PCI buses, called mb1 and mb2, on the router midplane. These buses provide a path to packet input/output (I/O) memory and the system (routing and switching) processor.
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Port adapters in odd-numbered slots connect to PCI bus mb1.
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Port adapters in even-numbered slots connect to PCI bus mb2.
It is important that you distribute the port adapters evenly between the two buses. This is because 7200 series routers have a data-carrying capacity—referred to as bandwidth—that affects the port adapter distribution in the chassis, as well as the number and types of port adapters that you can install.
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Cisco 7200 or Cisco 7200 VXR routers with an NPE-100, NPE-150, NPE-175, NPE-200, or NPE-225 use a high-, medium-, or low-bandwidth designation to determine port adapter distribution and configuration.
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Cisco 7200 VXR routers with an NPE-300, NPE-400, or a Network Services Engine (NSE-1) use bandwidth points to determine port adapter distribution and configuration (instead of high-, medium-, or low-bandwidth designations).
Bandwidth points are an assigned value related to bandwidth; however, the value is adjusted based on how efficiently the hardware uses the PCI bus. The PA-A1 aggressively uses PCI memory since it has only a small amount of cell FIFO memory. Thus, it is recommended that you avoid using more than two ATM high-speed interfaces in a Cisco 7200 router. Ensure that you place each ATM adapter in slots that use different PCI buses. More information on using port adapters in the Cisco 7200 is available in the Cisco 7200 Series Port Adapter Hardware Configuration Guidelines.
The PA-A1 has reached end of sales for NPEs that use Synchronous Dynamic RAM (SDRAM) for packet memory. In some cases, the PA-A1’s small amount of FIFO memory is not large enough to overcome memory access latencies on the SDRAM-based NPEs, if the PA-A1 must receive and transmit large frames simultaneously. This problem is documented in Cisco Bug ID CSCdm52201. SDRAM-based NPEs include the NPE-100, NPE-175, NPE-225, and NPE-300. Please contact Cisco Technical Support, if your router is experiencing these symptoms.
Note: Static-RAM-based (SRAM-based) NPEs include the NPE-150 and NPE-200; they use proprietary, triple-ported SRAM that provides very low access latency to the CPU and to the port adapters. These NPEs are not affected by the memory-access latency problems.
Memory Fallbacks and the PA-A1
Packet memory on the Cisco 7200 router and on the VIP2 is divided into particles that are 512 bytes in size. Cisco IOS Software creates a private, static particle pool for each interface and creates a public dynamic pool—called the normal pool—which all interfaces and processes share.
Some port adapters use the public pool particles as a fallback when the private interface pool is full. The PA-A1 does not use the fallback pool by design, because the fallback pool may not be from memory with very low access latencies. In other words, the PA-A1 does not try to find a public particle if it runs out of free private particles.
Issue the show buffers command to view the number of public particles and private particles. In this sample output from a Cisco 7206 with an NPE-200, the router allocated 400 private particles to the PA-A1 and allocates 1024 public particles to the normal pool:
Public particle pools: F/S buffers, 128 bytes (total 512, permanent 512): 0 in free list (0 min, 512 max allowed) 512 hits, 0 misses 512 max cache size, 512 in cache Normal buffers, 512 bytes (total 1024, permanent 1024): 1024 in free list (512 min, 2048 max allowed) 102371 hits, 0 misses, 0 trims, 0 created 0 failures (0 no memory) Private particle pools: ATM1/0 buffers, 512 bytes (total 400, permanent 400): 0 in free list (0 min, 400 max allowed) 400 hits, 102371 fallbacks 400 max cache size, 1 in cache
Known Issues
RxFREEZE Errors
Under rare conditions, typically following a burst of traffic, the PA-A1 reports an RxFREEZE condition in log messages:
May 21 18:32:44: %ATMPA-3-RxFREEZE: ATM4/0: receive freeze 813 May 21 18:36:19: %ATMPA-3-RxFREEZE: ATM4/0: receive freeze 814 May 21 18:42:36: %ATMPA-3-RxFREEZE: ATM4/0: receive freeze 815
Issue the show controllers atm command to view the Rx freeze counter:
router# show controllers atm 1/0 Interface ATM1/0 is up Hardware is TI1570 ATM slot 1, unit 0, subunit 0, fci_type 0x00000017, max_pak_size 4516 particle size 512, pool size 400, cache size 400, cache end 0 Fallback pool cache size 0, cache end 0 Rx free buf ring size 512, init buffers 400, current buffers 400 Rx max spin 128 Tx seg rings size 256, TX max spin 128, TX scheduler table size 48 enabled 0, disabled 0, throttled 0 vc_per_vp 1024, max_VP 6, max_vc 6144, total_vc 1 Rx cells 1256604332 hec error 0, aal5 discard 15606, unknown prot 38, unknown reg 0x100552B5 pkt overflow 0, crc error 0, no buf 8777, Rx freeze 11 timeout 0, abort 8, congestion_cell 0, Rx dma error 0 !--- Output suppressed.
The RxFREEZE message indicates that the ATM interface is overloaded and that the processor cannot sustain the amount of bursty traffic coming from the PA-A1. Normally, this condition is a temporary state that the router can correct.
To solve this problem, try these steps:
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Evaluate your network design.
Offload some traffic to a second ATM interface.
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Try replacing the PA-A1 with a PA-A3 (revision 2).
The PA-A1 has a very shallow receive cell FIFO and is not the best choice for heavy receive traffic or long bursts.
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Is the ATM interface recording an increasing number of input errors and aborts?
Upgrade to a faster NPE, NSE, or VIP2 with more host packet memory. The PA-A1 relies on such memory to reassemble packets.
False Throttles With Token Ring PA
Cisco bug ID CSCdm78604 resolves a problem with Token Ring port adapters generating false throttles on an ATM interface in the same Cisco 7200 series router. Symptoms include many throttles and very few or no input drops on the ATM interface.
Related Information
| Updated: Nov 15, 2007 | Document ID: 10481 |